CERAMIC PACKAGING INTEGRATED CIRCUITS

Brand	Owner	Address	Description
DI PAK	DIELECTRIC LABORATORIES, INC.	2777 ROUTE 20 EAST CAZENOVIA NY 13035	Ceramic packaging for integrated circuits and electronic devices, namely, transistors, transducers and combinations thereof;DYE PACK;PAK;
	Where the owner name is not linked, that owner no longer owns the brand

Technical Examples

Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.