COMPUTER COMPONENTS INSTRUCTION MANUALS

Brand Owner (click to sort) Address Description
CORSAIR CORSAIR MEMORY INC. 47100 Bayside Parkway Fremont CA 94538 Computer components and instruction manuals packaged and sold as a unit therewith, namely, memory modules, power supply units, solid-state drives, liquid-cooling solutions for CPUs and memory modules, air-cooling solutions for CPUs and memory modules, fans, and cases and enclosures for computers; computer peripherals, computer hardware, and instructions manuals packaged as a unit therewith, namely, USB flash drives, external solid-state drives, mice, keyboards; computer peripherals, computer hardware, and instruction manuals packaged as a unit therewith, namely, [ joysticks, game controllers, steering wheels, flight controllers, and ] specialized mice and keyboards used as input devices for computer games and console games; computer hardware, and instruction manuals packaged as a unit therewith, namely, headsets, headphones [, and multimedia speakers ];
VENGEANCE CORSAIR MEMORY INC. 47100 Bayside Parkway Fremont CA 94538 Computer components and instruction manuals packaged and sold as a unit therewith, namely, power supply units, [ liquid-cooling solutions for CPUs and memory modules, air-cooling solutions for CPUs and memory modules, ] fans, and cases and enclosures for computers; computer peripherals, computer hardware, and instruction manuals packaged as a unit therewith, namely, [ joysticks, game pads, game controllers, steering wheels, flight controllers, and ] specialized mice and keyboards used as input devices for computer games and console games; computer hardware, and instruction manuals packaged as a unit therewith, namely, headsets, headphones, earphones [, and multimedia speakers ];
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.