FIFTY FABULOUS

Brand Owner (click to sort) Address Description
50 & FABULOUS The Sterling James Company 4786 Guernsey Loop Castle Rock CO 80109 FIFTY AND FABULOUS;Caps being headwear; Sashes; Shirts; Tank tops; Yoga pants;Coffee mugs; Drinking glasses; Drinking straws; Insulating sleeve holders for beverage cans; Paper plates; Plastic cups; Shot glasses;
50 & FABULOUS Paris Products Co. 3010 Brighton Sky Ln. Katy TX 77494 FIFTY AND FABULOUS; FIVE ZERO AND FABULOUS;Bottles, sold empty; Containers for household use; Drinking glasses, namely, tumblers; Household containers for foods; Jugs; Mugs; Non-electric portable beverage coolers; Wine aerators; Wine jugs; Wine pourers; Wine strainers; Wine tasters; Cups; Dinnerware; Drinking bottles for sports; Drinking straws; Kitchen containers; Oven mitts; Rags for cleaning; Thermal insulated bags for food or beverages; Trays for domestic purposes; Water bottles sold empty; Washing brushes; coasters not of paper or textile; Insulating sleeve holders for beverage cans; Cocktail shakers; flasks; ice buckets; shot glasses; tumblers for use as drinking glasses; wine glasses; drinking glasses, namely, whiskey glasses; plastic cups;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.