FLAGS BANNERS MADE

Brand Owner (click to sort) Address Description
ALL NATIONS FLAG CO., INC. All Nations Flag Co., Inc. 118 W. 5th Street Kansas City MO 64105 flags and banners made of cloth;FLAG CO., INC.;
DU PONT REFINISH RACING E. I. DU PONT DE NEMOURS AND COMPANY 974 Centre Road Wilmington DE 19805 flags and banners made of paper;flags and banners made of cloth;
DUPONT REFINISH RACING E. I. DU PONT DE NEMOURS AND COMPANY 974 Centre Road Wilmington DE 19805 flags and banners made of cloth;
FLANNER ZEPHYRSMITH DESIGNS, INC. 20410 SWEETBRIAR ROAD WEST LINN OR 97068 flags and banners made of cloth;
FLYING COLOURS USA, INC. Flying Colours USA, Inc. 485 North Main Street Glen Ellyn IL 60137 flags and banners made of canvas and/or sheets and laminates of man-made fibers (Tyvek);flags and banners made of nylon, vinyl and/or polyethylene;
HOPE ARKANSAS EST. 1875 City of Hope 1500 East Duarte Road Duarte CA 91010 flags and banners made of cloth;HOPE ARKANSAS and EST. 1875;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed. Exemplary gate logic synthesized using the aforementioned methods, and a computer system capable of implementing these methods, are also described.