INTEGRATED SYSTEM COMPUTER HARDWARE

Brand Owner (click to sort) Address Description
FASTTRACK FASTECH, INC. 1551 Central Street Stoughton MA 02072 integrated system of computer hardware, software and peripherals that link remote field portable computer users to central data facilities for use in collecting, organizing, processing, presenting, analyzing and distributing field and central data facilities data, especially sales-activity related information;FAST TRACK;
INTERNET PROVIDER ACCESS CONTROLLER TECHNOLOGY APPLICATIONS, INC. 5303 Spine Rd., Ste. #101 Boulder CO 80301 integrated system of computer hardware components and computer software modules which, together, operate as a full function Internet server;INTERNET, ACCESS or PROVIDER;
IPAC TECHNOLOGY APPLICATIONS, INC. 5303 Spine Rd., Ste. #101 Boulder CO 80301 integrated system of computer hardware components and computer software modules which, together, operate as a full function global computer network server, but specifically excluding coatings for (i) computer hardware components, (ii) electronic components, and (iii) fiber optic cables;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. Disclosed is a control device for preventing hardware strapping fault of a computer system. The computer system includes a central processing unit having a first signal pin, an integrated circuit device having at least one hardware strapping pin, and an external device coupled to the computer system and having a second signal pin. The hardware strapping pin is a multiplexing pin that generates a hardware strapping signal to the central processing unit to perform a hardware strapping operation at the time when the system is being powered on and, after the hardware strapping is completed, is connectable to the second signal pin of the external device. The control device includes a hardware strapping fault prevention circuit coupled between the hardware strapping pin of the integrated circuit device and the second signal pin of the external device to isolate the second signal pin of the external device from the first signal pin of the central processing unit at the time when the system is being powered on.