MULTI PORT SWITCHING DEVICES INCORPORATING PROCESSORS

Brand Owner (click to sort) Address Description
ETHERCHANNEL CISCO TECHNOLOGY, INC. 170 West Tasman Drive San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;
ETHERCHANNEL KALPANA, INC., A SUBSIDIARY OFCISCO SYSTEMS, INC. 170 West Tasman Drive San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;
ETHERSWITCH CISCO TECHNOLOGY, INC. 170 West Tasman Drive San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;ETHER SWITCH;
HUBSWITCH Kalpana, Inc. 125 Nicholson Lane San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;
KALPANA Kalpana, Inc. 125 Nicholson Lane San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;
SERVERSWITCH Kalpana, Inc. 125 Nicholson Lane San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;SERVER SWITCH;
THE SWITCH IS THE HUB Kalpana, Inc. 125 Nicholson Lane San Jose CA 95134 multi-port switching devices incorporating processors for use with local area networks;
TOKENSWITCH KALPANA, INC., A SUBSIDIARY OF CISCO SYSTEMS, INC. 170 WEST TASMAN DRIVE SAN JOSE CA 95134 multi-port switching devices incorporating processors for use with local area networks;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. The present invention provides a method and system of interconnecting L processors of a parallel computer to facilitate torus partitioning, (a) where each of the processors includes a processing unit and a switch, (b) where the switch includes a first external port, a second external port, a third external port, a fourth external port, a first internal port, and a second internal port, (c) where the L processors comprise R non-overlapping partitions, (d) where each of the partitions comprises the processing unit of at least one of the processors, and (e) where L is an integer ?2 and R is an integer ?1. In an exemplary embodiment, the method and system include connecting the L switches of the L processors among the external ports of the L switches in an extended torus architecture and setting the connected L switches thereby interconnecting each of the partitions as a torus.