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Technical Examples
A pulse generator electrical circuit capable of operating as both a clock-based pulse generator and a delay-based pulse generator while minimizing the limitations of these two types of pulse generators is disclosed. When the pulse generator operates in "delay mode," the smallest output pulse width possible corresponds to the minimum set point delay between the two delay circuits. The largest possible output pulse width corresponds to the difference between the maximum and minimum of the delay circuits. When the pulse generator operates in "clock mode," the output of one of the delay circuits is blocked so that the output of the gate depends solely on the output of other delay circuit. This limits the lower pulse width interval to that of the retimer clock, but allows for an arbitrarily long (wide) pulse.