REWARDS BASED PROMOTION

Brand Owner (click to sort) Address Description
REACHING THE FREQUENT DINER RTR Funding Two N. Riverside Plaza, Suite 200 Chicago IL 60606 rewards-based promotion, advertising and marketing services directed to merchants, including restaurants, entertainment venues, retailers, personal services providers, and hotels; providing merchant information in the field of restaurants, entertainment venues, retailers, personal services providers, and hotels to consumers via on-line, electronic mail and print communications; providing incentive award programs for customers and employees through the distribution of frequent flyer miles or credit card, debit card reimbursement, for the purpose of promoting and rewarding loyalty;FREQUENT DINER;
YOUR VISION. OUR MEMBERS. YOUR SUCCESS. RTR Funding Two N. Riverside Plaza, Suite 200 Chicago IL 60606 Rewards-based promotion, advertising and marketing services directed to merchants, including restaurants, entertainment venues, retailers, personal services providers, and hotels; on-line business directories featuring information about local merchants intended for use by consumers; and customer loyalty services and customer club services, for commercial, promotional and advertising purposes;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.