ETCHING PROCESS SEMICONDUCTOR WAFER

Brand	Owner	Address	Description
VIPACK	Advanced Semiconductor Engineering, Inc.	26, Chin 3rd Road Nantze Export Processing Zone Nantze Kaohsiung 811 Taiwan	Etching process of semiconductor wafer; semiconductor packaging processing; etching processing of integrated circuits; semiconductor wafer-level processing; wafer foundry; integrated circuit packaging processing; manufacture of substrates, seminconductors, integrated circuits, integrated circuit boards, and wafers specified by the customer;The mark consists of the word VIPACK to the right of various lines.;Color is not claimed as a feature of the mark.;Technology research and development for others in the field of semiconductor related product; integrated circuits design; semiconductor packaging design; substrate design; quality inspection for semiconductors and the related products; testing of semiconductors and the related products; quality identification for semiconductors and the related products; consulting with respect to semiconductor packaging technology;
	Where the owner name is not linked, that owner no longer owns the brand

Technical Examples

A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second etching process is executed with an etchant comprising oxygen to etch the doped semiconductor layer and the semiconductor layer, and the first resist layer undergoes ashing during etching so as to become a second resist layer with a channel pattern. The third etching process is another wet etching, and the second conducting layer is etched again using the second resist layer as the etching mask. The fourth etching process is executed to dry etch the doped semiconductor layer using the second resist layer as the etching mask.