ETCHING PROCESSING SEMICONDUCTOR

Brand Owner Address Description
A-EASI Advanced Semiconductor Engineering, Inc. 26, Chin 3rd Road Nantze Export Processing Zone Nantze Kaohsiung 811 Taiwan Etching processing in the semiconductor wafer; manufacture of semiconductor, Integrated circuit, Integrated circuit board and wafer specified in the standard from customers; semiconductor packaging processing in the nature of manufacturing services for others; etching processing in integrated circuits; semiconductor wafer-level processing; wafer foundry, namely, manufacturing of semiconductor wafers for others; integrated circuit packaging processing in the nature of manufacturing services for others; semiconductor substrate processing and manufacturing; substrate foundry, namely, manufacturing of semiconductor substrates for others; manufacture of semiconductor substrate;Semiconductor device, Product featuring semiconductor package, namely, computer hardware in the nature of wireless access point devices; wafer level package comprising silicon wafers, structured semiconductor wafers, integrated circuits; integrated circuits that contain metal bumps; semiconductor substrate;A-EASY;Semiconductor related products technology research and development for others; Semiconductor packaging design; Integrated Circuit design; semiconductor substrate design; Quality inspection for semiconductors and related products; Testing for semiconductors and related products; quality identification for semiconductors and related products, namely, quality control for others;
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second etching process is executed with an etchant comprising oxygen to etch the doped semiconductor layer and the semiconductor layer, and the first resist layer undergoes ashing during etching so as to become a second resist layer with a channel pattern. The third etching process is another wet etching, and the second conducting layer is etched again using the second resist layer as the etching mask. The fourth etching process is executed to dry etch the doped semiconductor layer using the second resist layer as the etching mask.